OKI Develops 124-Layer PCB Technology
OKI developed a 124-layer PCB technology for AI semiconductor wafer inspection equipment, increasing layer count by 15% over previous 108-layer designs.
summary is enough The announcement is a straightforward incremental upgrade for specialized industrial equipment, with limited technical depth in the article.
summary
OKI Circuit Technology has developed a 124-layer PCB with a fixed thickness of 7.6 mm, specifically for testing next-generation High Bandwidth Memory (HBM) on wafers. The technology uses ultra-thin materials and a proprietary automatic transport system to increase signal density. This allows for the high-speed, high-frequency data transfer required to test miniaturized AI semiconductors before they are packaged.
key points
- The PCB maintains a 7.6 mm thickness while increasing layers from 108 to 124.
- Designed specifically for HBM wafer inspection, where thousands of connections per chip must be routed to testing circuits.
- Mass production is targeted for October 2025 at the Joetsu Plant in Niigata Prefecture.
who should read it
Hardware engineers and semiconductor testing equipment manufacturers.
discussion mixed
consensus
Commenters generally view this as an incremental improvement rather than a breakthrough. Much of the discussion focuses on the others' nostalgia for old OKI printers and the impracticality of building CPUs from PCBs.
pushback
Some users question the signal integrity of such a high layer count, while others argue that intelligent routing tools can mitigate these issues.
They state it's for HBM wafer inspection equipment:
OKI Group printed circuit board (PCB) company, has successfully developed 124-layer PCB technology for wafer inspection equipment designed for next-generation high bandwidth memory, such as HBM
Since the latest semiconductors process an enormous number of signals and the number of wafer-mounted chips increases due to process miniaturization, it is necessary to increase density and more layers on the PCBs used in inspection equipment.
In their linked semiconductor testing page[1], they mention conductive paste. So seems they test whole …
It provides a detailed technical explanation of why HBM testing requires such high layer counts due to the 1024-2048 bit bus widths.
Generated by an LLM from the article and thread. Check the sources before relying on it.