Recreating Voodoo Graphics and a Late-1990s Gaming PC on an FPGA

summary

The author successfully implemented a SystemVerilog version of the 3dfx Voodoo Graphics (SST-1) chip, called zSST, and integrated it with a z486 CPU to create a functional late-90s DOS PC on a Xilinx KV260 board. While the arithmetic rendering pipeline was relatively straightforward to build, the primary challenge was overcoming the high latency of shared DDR memory compared to the original card's dedicated EDO RAM. This was solved by implementing a texture cache, a replay queue for outstanding requests, and a reorder buffer to maintain pixel processing order.

key points

1. The zSST implementation covers most core Voodoo features, including texture filtering, mipmapping, depth/alpha tests, and fog, allowing original Glide-based games like Tomb Raider to run on FPGA hardware.
2. The original Voodoo hardware used a clever interleaving pattern across multiple EDO RAM chips to ensure that the four texels needed for bilinear filtering could be fetched in parallel without conflict.
3. To adapt the design to the KV260's shared memory architecture, the author used a 8 KiB texture cache and a 64-entry reorder buffer, allowing the pipeline to perform useful work while waiting for high-latency DDR memory responses.

who should read it

Hardware enthusiasts, FPGA developers, and retro-computing historians interested in the detailed implementation of early 3D graphics acceleration and memory architecture.

discussion warm