Speeding up gearhash on ARM64

summary

The gearhash Rust crate has been updated to include a NEON backend for ARM64, achieving nearly twice the speed of the scalar implementation. This improvement was reached by overcoming serial dependency chains and reducing instruction counts through SIMD parallelization and strategic unrolling. The optimization process involved shifting from a latency-bound approach to a throughput-bound one, ensuring high performance on modern ARM64 hardware like Apple M-series and AWS Graviton chips.

key points

1. The author overcame the serial nature of the GEAR rolling hash by recognizing that the hash state is completely replaced every 64 bytes, allowing the input to be split into parallel strips for SIMD processing.
2. Initial NEON ports were slower than scalar code due to loop-carried latency; this was fixed by precomputing table entries and using 'naughty' scalar combining to prevent the compiler from reassociating additions back into the dependency chain.
3. Performance was further improved by replacing multiple byte loads with a single 32-bit load and combining four boundary tests into a single vector operation to minimize costly moves from the vector unit to general-purpose registers.

who should read it

Software engineers and performance optimization experts, particularly those working with content-defined chunking or Rust on ARM64 architectures.

discussion skeptical